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eigenbau:currentstabilisation:start [2020/02/07 10:13] – [Schematic] fiene | eigenbau:currentstabilisation:start [2020/02/07 10:24] (current) – [Input Signals] fiene | ||
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* All files can be found on http:// | * All files can be found on http:// | ||
* {{ : | * {{ : | ||
- | * Die Source des Schaltplans ist auf der [[eigenbau: | + | * Die Source des Schaltplans ist auf der [[eigenbau: |
==== Layout ==== | ==== Layout ==== | ||
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Up to now only PID A is populated (exept D) after Hacking the logic at the S&H IC, it works as expected. after switching in hold mode, the current seems to be a bit lower than the initial setpoint. this might be caused by the big hold capacitor. Maybe after 0.5 sec. it is not entirely loaded. The hold time seems to be huge, after 30s there is almost no change visible, seems to be a fraction of a Millivolt. So it might be an option to change the Cap to a smaller one, leading to a smaller hold time, but a more precise hold value. | Up to now only PID A is populated (exept D) after Hacking the logic at the S&H IC, it works as expected. after switching in hold mode, the current seems to be a bit lower than the initial setpoint. this might be caused by the big hold capacitor. Maybe after 0.5 sec. it is not entirely loaded. The hold time seems to be huge, after 30s there is almost no change visible, seems to be a fraction of a Millivolt. So it might be an option to change the Cap to a smaller one, leading to a smaller hold time, but a more precise hold value. | ||
- | The idea of having the current on for a longer time before switching to hold mode didn' | + | The idea of having the current on for a longer time before switching to hold mode didn' |
FIXME /* Welche Signale sollten wo zu sehen sein? */ | FIXME /* Welche Signale sollten wo zu sehen sein? */ | ||
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^ Input ^ Type ^ Description | ^ Input ^ Type ^ Description | ||
- | | ULTRASTAB (D-SUB) | + | | ULTRASTAB (D-SUB) |
| Current set | analog voltage (differential) | | Current set | analog voltage (differential) | ||
| enable | | enable |